1. Field of the Invention
The present invention relates to a semiconductor device, and especially to a negative voltage generating circuit and a detector circuit provided therein.
2. Description of the Background Art
Usually, a semiconductor device including a DRAM (Dynamic Random Access Memory) is provided with negative voltage generating circuitry for generating a voltage that is negative and lower than the ground (GND) potential (hereinafter referred to as a negative voltage). The negative voltage is used as a substrate bias potential and controls the transistor substrate effect. For example, in a DRAM that uses a PMOS transistor as a memory cell transfer gate, the negative voltage is used as a voltage for driving the transistor (activation voltage). It is necessary to set the transistor driving voltage sufficiently low, in order to write a ground-level signal to the memory cell during write and to extract a signal voltage with a sufficient amplitude from the memory cell during read.
In general, when a negative voltage generated by a negative voltage generating circuit is used as a substrate bias potential, potential variations are suppressed by large capacitance of the substrate, and the negative voltage generating circuit is not required to provide high-speed response. However, when the semiconductor device using the negative voltage as a transistor driving voltage is operated at high speed, the current consumption related to the negative voltage is large and therefore high-speed response of the negative voltage generating circuit is needed. Steadily supplying the negative voltage even when the current consumption related to the negative voltage is large requires quickly detecting potential variations of the negative voltage and feeding power (supplying charge).
Conventional negative voltage generating circuits are disclosed in Japanese Patent Application Laid-Open Nos. 10-239357 (1998) and 11-312392 (1999), for example. The negative voltage generating circuit described in Japanese Patent Application Laid-Open No. 10-239357, for example, includes a charge pump circuit for generating a negative voltage and a detector circuit for detecting the potential of the negative voltage (which is referred to also as “a negative voltage sensing circuit” or “a level detecting circuit”). When detecting the negative voltage becoming higher than a desired value because of current consumption, the detector circuit activates the charge pump circuit to supply charge to the negative voltage output so that the negative voltage keeps the desired value.
In conventional negative voltage generating circuits, the detector circuits do not have high-speed response. Accordingly, when the semiconductor device using the negative voltage as a transistor driving voltage is operated at high speed, the detector circuit may fail to sufficiently follow instantaneous variations of the negative voltage, which leads to unstable supply of the negative voltage.
Also, breakdown voltages of semiconductor devices are becoming lower because of recent downsizing of LSIs, i.e., miniaturization of transistors, which unavoidably leads to lower operating voltages (power-supply voltages). Moreover, battery-driven portable devices, for example, demand reduction of power consumption through reduction of operating voltage and reduction of consumption current. However, lower operating voltage further deteriorates the detector circuit response and reduces the stability of the negative voltage generating circuit. This hinders reduction of power consumption of the semiconductor devices.